1. Field
Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a method of wafer burn-in test and a semiconductor memory device for the same.
2. Description of the Related Art
An analysis of defective semiconductor products shows a high failure rate early in the products' life followed by stabilization. In order to stabilize the failure rate of early stage semiconductor products, the products are stressed in advance. Stressing the packaged semiconductor product requires exposure to high temperatures for a long duration, a process referred to as a burn-in test.
As the capacity of semiconductor memory increases, more time is required to complete the burn-in test for package level semiconductor products. To reduce the total amount of time required to conduct the burn-in test, the semiconductor product completes two burn-in tests, once at a wafer level and again at a package level. During the wafer burn-in test, the semiconductor memory is stressed with a high voltage supply and long-term exposure to high temperatures.
During the wafer burn-in test, all of the cell transistors are simultaneously turned on because the wafer burn-in test is not for checking normal operation of each cell in the wafer but for stressing the wafer out. To simultaneously turn on all of the cell transistors, the wafer is given high peak current. When the amount of peak current is not large enough, all of the cell transistors may not be simultaneously turned on and the wafer may not be fully stressed, resulting in an incomplete or failed wafer burn-in test.
Causes of early stage product failure may exist on defects in the dielectric structure, i.e., oxide between adjacent word lines as well as oxide between a gate and a channel.
A memory cell array is the smallest unit of cell groups in the semiconductor memory. The memory cell array includes a plurality of word lines, disposed within a certain interval, and a plurality of bit lines disposed within a certain interval, with the plurality of bit lines being perpendicular to the plurality of word lines. The memory cell array includes a normal cell, from which data is to be written and read during operation of the memory cell, and a dummy cell disposed outside the normal cell area for protecting the normal cell from external interference. Dummy cells include an upper set of dummy cells, each of which is connected at its gate to an upper dummy word line disposed at the upper border of the memory cell array, and a lower set of dummy cells, each of which is connected at its gate to a lower dummy word line disposed at the lower border of the memory cell array.
During normal semiconductor memory operation, all of the dummy word lines are provided with a negative word line voltage or a pumping voltage in a specific mode. The dummy word lines are not individually controlled but are provided with a single voltage. The memory cell array may have one or more upper dummy word lines and one or more lower dummy word lines. Biases of all the dummy word lines are combined and thus all of the dummy word lines may have the same signal.
Therefore, when odd word lines and even word lines are alternatively activated, or every Nth word line is activated during the wafer burn-in test, a normal cell right next to the dummy word lines, which are biased to a constant level, is not stressed enough.
Causes of early stage product failure may exist on defects in the gate oxide of a cell as well as in oxide between the cells. To detect such defects between cells, a bit line and the adjacent bit line are to have different voltages from each other. Therefore, upper and lower bit line sense and amplification units (BLSA) are provided with bit line precharge voltages, which are different from each other, in response to a bit line equalization signal. However, the dummy word lines cannot be individually controlled because the biases of the dummy word lines are combined and all the dummy word lines may have the same signal.
Therefore, when the bit line precharge voltages are alternatively activated, an equalized stress may not be applied to the normal cells and the dummy cells and early stage product failure may not be detected. Reliability of the semiconductor product is greatly affected by the wafer burn-in test for detecting early stage product failure.